P-code Generator FPGA Design for Direct GPS P (Y)-Code Acquisition

Direct GPS P (Y)-code acquisition is necessary when GPS C/A code signal is denied. Since the acquisition process is a two-dimensional search in time domain and frequency domain, a successful correlator design with a local P-code generator as reference is very important. As a new programmable technology, FPGA is a good choice for digital system prototyping and design. Especially Xilinx Virtex chip DLL feature is appropriate for GPS application since GPS is a time based ranging system. However, due to the extremely long sequence of P-code, it is a challenging task to efficiently design and verify Pcode generator using HDL (hardware description language) and commercial CAD tools. In this paper, an equivalent GPS P-code simulator model is proposed to facilitate design and verification. In addition, a group of mathematical equations are developed to implement a flexible P-code generator, which can start running from any specific time of a week. As a result, it can be extended to massive parallel correlator design for direct GPS P (Y)code acquisition application.